1. Field of the Invention
The present invention relates to bottom-gate thin-film transistors and methods for making the same, and also relates to liquid crystal display devices and organic EL devices using the bottom-gate thin-film transistors.
2. Description of the Related Art
Thin-film transistors (TFTs) are generally used as switching elements in active matrix liquid crystal display devices, active matrix organic EL display devices, etc. Thin-film transistors fall into two broad categories: a bottom-gate type and a top-gate type. In the bottom-gate thin-film transistor, a gate electrode is disposed below an active layer, and the bottom-gate thin-film transistor has superior reliability in comparison with the top-gate thin-film transistor. Additionally, structures of bottom-gate thin-film transistors are described in detail, for example, in MODERN LIQUID CRYSTAL PROCESS TECHNOLOGY '99 (Press Journal, 1998, pp.53 to 59), FLAT PANEL DISPLAY 1999 (Nikkei BP, 1998, pp.132 to 139), and Japanese Unexamined Patent Application Publication No. 8-279618.
FIG. 6 is a schematic sectional view of a liquid crystal display device using a conventional bottom-gate thin-film transistor, and FIGS. 7A to 7G and FIGS. 8H to 8L show the steps for fabricating the liquid crystal display device.
In the fabrication process, first, a gate electrode 2 composed of a metal, such as Cr, Al, Mo, or Ta, is formed, with a thickness of approximately 200 nm, on a transparent glass substrate 1, and a Cs electrode 3 is similarly formed, as shown in FIG. 7A.
A gate insulating film 6 is deposited on the gate electrode 2, and the gate insulating film 6, for example, consists of a silicon nitride film 4 with a thickness of 50 nm and a silicon oxide film 5 with a thickness of 150 nm. After the gate insulating film 6 is deposited, an amorphous silicon film is continuously deposited with a thickness of 50 nm. The amorphous silicon film is then crystallized by thermal annealing with an infrared lamp, laser annealing, or the like to form a polysilicon film 7, as shown in FIG. 7B.
Next, a protective insulating film 8 composed of a silicon oxide is formed with a thickness of 200 nm, as shown in FIG. 7C. A resist is placed on the protective insulating film 8, and by exposure from the back surface using the gate electrode 2 as a mask, the resist is patterned on a channel-forming section self-aligned with the gate electrode 2. The protective insulating film 8 is removed by etching using the resist as a mask so that the protective insulating film 8 remains in the channel-forming section self-aligned with the gate electrode 2, as shown in FIG. 7D. In the etching process, hydrofluoric acid-based wet etching or fluorine-based dry etching is usually used.
Next, ions, such as phosphorus ions or arsenic ions, are implanted using the protective insulating film 8 composed of the silicon oxide as a mask, to form a lightly doped drain (LDD) region 9, as shown in FIG. 7E. Next, an N-channel source-drain-injection resist mask (SD-injecting mask) 11 is formed using a resist or the like, and the protective insulating film 8 on the polysilicon film 7 in a source-drain region (SD region) and in an auxiliary capacitor region comprising the polysilicon film 7 and the gate electrode 2 is removed by hydrofluoric acid-based wet etching or fluorine-based dry etching, as shown in FIG. 7F. An N-channel source-drain region (SD region) 10 is then formed by injection of phosphorus, arsenic, or the like at high concentration. Furthermore, in order to activate the dopant, such as the injected phosphorus, thermal annealing or laser annealing is performed so that the non-doped portion of the polysilicon film 7 constitutes an active layer, and thus a TFT 100 is obtained, as shown in FIG. 7G.
Next, a resist is placed on the section of the substrate 1 having the TFT 100, and unwanted portions of the protective insulating film 8 and the polysilicon film 7 are patterned, as shown in FIG. 8H. In such a case, etching of the protective insulating film 8 is usually performed by hydrofluoric acid-based wet etching or fluorine-based dry etching. Etching of the polysilicon film 7 is often performed by F-based or Cl-based dry etching.
Next, in order to form an interlayer insulating film 13, a silicon nitride film 14 (300 nm) and a silicon oxide film 15 (200 nm) are continuously deposited, as shown in FIG. 8I.
The interlayer insulating film 13 and the gate insulating film 6 are removed by etching at a contact-forming section on the polysilicon film 7 and a contact-forming section (not shown in the drawing) on the gate electrode 2, and thus contact holes 16 are made, as shown in FIG. 8J. By embedding a metal, such as Al, in the contact holes 16, a source electrode 17 and a drain electrode 18 are formed, as shown in FIG. 8K.
Next, a planarizing layer 19 composed of an organic planarizing film, a silicon nitride planarizing film, or the like is formed in the region excluding a section for forming a contact with a transparent electrode of the liquid crystal display panel and a pad-forming section. A transparent electrode 20 composed of ITO or the like is then formed so as to cover the pixel section, and an alignment layer 21 is formed on the transparent electrode 20. Thus, a TFT substrate 201 is obtained, as shown in FIG. 8L.
A liquid crystal display device 200 shown in FIG. 6 has a panel structure including the thus-obtained TFT substrate 201, a counter substrate 203 provided with a counter electrode 202, and a liquid crystal 204 interposed between both substrates.
In the TFT 100 used in the conventional liquid crystal display device shown in FIGS. 6 to 8L, the auxiliary capacitor is constructed by the polysilicon film 7 doped with phosphorus or the like at high concentration and the Cs electrode 3 (the same layer as that of the gate electrode 2), and in order to form such a shape, the protective insulating film 8 on the polysilicon film 7 must be removed by etching twice, as shown in FIGS. 7D and 7F. Therefore, a complex process is required, thus preventing an improvement in productivity.
Additionally, in the region in which the protective insulating film 8 is removed by the first etching (refer to FIG. 7D), the polysilicon film 7 is exposed from the beginning in the step of removing the protective insulating film 8 by the second etching (refer to FIG. 7F). At this stage, since the polysilicon film 7 has been transformed into the LDD region 9 in which the N-channel is formed by implantation of phosphorus ions, arsenic ions, or the like, pinholes, etc. easily occur due to corrosion by an alkaline resist stripper and a hydrofluoric acid-based etchant. Consequently, the polysilicon film 7 in this section and the gate insulating film 6 (the silicon oxide film 5, in particular) therebelow may be etched by the hydrofluoric acid-based etchant, resulting in a decrease in the breakdown voltage of the gate insulating film 6 between the polysilicon film 7 and the Cs electrode 3 (or the gate electrode 2).